1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage apparatus and a method of driving the same, and more particularly to a driving operation of an electrically writable/erasable nonvolatile semiconductor storage apparatus capable of storing information of 2 bits or more in one memory cell.
2. Description of the Related Art
An electrically writable/erasable nonvolatile semiconductor storage apparatus (flash memory) has spread for storing a program code. In recent years, in addition to the uses, uses for storing mass data such as image data, voice data or animation data have been demanded and a further increase in a capacity has been required.
In a system such as a cell phone, moreover, there has been demanded a flash memory capable of implementing, in one chip, a storage of a program code demanded to have an increase in a reading speed and various data required to have an increase in a capacity in order to reduce a mounting region and a cost by a decrease in the number of components.
As a technique for implementing a further increase in a capacity of a flash memory, attention has been paid to a technique for a multivalue in addition to the microfabrication of a semiconductor processing technique.
In case of an ordinary binary flash memory, a threshold of a memory cell is set into two states, and a high state is caused to correspond to “0” (or “1”) and a low state is caused to correspond to “1” (or “0”).
On the other hand, a four-valued flash memory will be considered as an example of a flash memory using the multivalue technique. Referring to a flash memory for storing 2-bit information in one memory cell, a conventional reading method of the flash memory using the multivalue technique will be described below with reference to FIGS. 10, 11, 12 and 13.
In reading, usually, when a power supply is turned ON (Step 1001) and a reading address is input (Step 1002), a memory cell corresponding to the reading address is selected (Step 1003) and a reading operation is carried out (Step 1004) as shown in a flowchart of FIG. 10.
In FIG. 11, characteristic curves 1101, 1102, 1103 and 1104 indicate Ids-Vgs characteristics in each threshold of the memory cell.
In the four-valued flash memory, a state in which “1” is stored in an address A1 and “1” is stored in an address A2 is set to be a state of the smallest threshold shown in the characteristic curve 1101.
In ascending order of the threshold, subsequently, a state in which “1” is stored in the address A1 and “0” is stored in the address A2 is set to be a threshold of the characteristic curve 1102, a state in which “0” is stored in the address A1 and “0” is stored in the address A2 is set to be a threshold of the characteristic curve 1103, and a state in which “0” is stored in the address A1 and “1” is stored in the address A2 is set to be a threshold of the characteristic curve 1104.
Referring to the reading operation of the multivalued flash memory thus set, for example, as shown in a voltage transition 1201 of Vgs-t of FIG. 12, a gate-source voltage of the memory cell is raised stepwise in order of Vgs1, Vgs2 and Vgs3, and it is decided whether a current Ids between a drain and a source which flows to the memory cell in an input of each Vgs is larger or smaller than a preset current and the decision is read. In case of such a reading operation, a correspondence of a result of a decision of a state in which the current flows (ON state) and a state in which the current does not flow (OFF state) in the input of each Vgs to information stored in the addresses A1 and A2 is shown in a table of 1202.
As another means for the reading operation of the multivalued flash memory, for example, a transition is carried out as shown in a voltage transition 1301 of Vgs-t in FIG. 13. Consequently, a correspondence of the result of the decision of the ON state and the OFF state which is obtained in the input of each Vgs to the information stored in the addresses A1 and A2 is shown in a table 1302 in the same manner as in the table 1202 of FIG. 12. More specifically, it is possible to decide whether data in the address A1 are “1” or “0” by deciding a current obtained when Vgs2 is input. By deciding currents when Vgs3 and Vgs1 are input, then, it is decided whether data in the address A2 are “1” or “0”.
As described above, various methods can be proposed for the reading operation of the multivalued flash memory. In the case in which 2-bit information in the addresses A1 and A2 are read, it is necessary to change the voltage Vgs three times and to decide the current in the method described with reference to FIG. 12, and to change the voltage Vgs twice at a maximum and to decide the current in the method described with reference to FIG. 13. For this reason, a reading speed is limited, and there is a problem in the case in which a program code requiring a high speed reading operation and various data requiring an increase in a capacity are stored in one memory cell array, for example.
In order to enhance a reading performance and a reading reliability, moreover, it is possible to improve the performance by setting a voltage difference in each threshold storing information to be great. In the multivalued flash memory, it is hard to maintain the voltage difference in the threshold thus set as compared with the binary flash memory.
As means for solving these problems, JP-A-2001-210082 Publication has disclosed a method of implementing, in one memory cell array, a program code requiring a high reading speed and various data requiring a large capacity by using, as a binary flash memory, a memory cell in a region requiring a high speed reading performance and using, as a multivalued flash memory, a region requiring a large capacity.
In the case in which the multivalued flash memory is used, it is necessary to change a Vgs voltage of a memory cell plural times in order to read a large number of bits stored in one memory cell, and furthermore, to decide a current. For this reason, a reading speed is reduced.
On the other hand, in a method using, as a binary flash memory, a region requiring a high speed reading operation and using, as a multivalued flash memory, a region requiring a large capacity, it is possible to suppress a reduction in the reading speed. In the region for the use as the binary flash memory, 1-bit information is stored. Consequently, a using efficiency of a memory cell array is reduced so that an increase in a chip area cannot be avoided.